Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 8/29/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.08.29 23.2
  • Updated Ethernet Subsystem Intel FPGA IP Features table in Supported Features section.
    • 200GbE GAUI-8 for F-Tile device.
  • Added Device Family Support section.
  • Updated Release Information section.
  • Added 200GbE GAUI-4/200GbE GAUI-8 port in Feature Description.
  • Updated Supported Ethernet Features table in Supported Features.
  • Added Enable ECC protection parameter in General Configuration tab.
  • Added the following parameters in Port_<port_number:1-16>Port_<n>_configuration of Ethernet Subsystem Intel FPGA IP Parameters: HSSI
    • Dynamic Reconfiguration
    • 100G Partial Reconfiguration
  • Added the following parameters to General Options in F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem –IP Configuration Tab table.
    • Enable debug endpoint for transceiver toolkit

    • Enable debug endpoint for Ethernet toolkit

    • Enable asynchronous adapter clocks
    • Enable dedicated CDR clock output
    • Include 40GE
    • Include 32bit sof CWBIN counters
  • Added AN channel location 0 under ANLT Options tab.
  • Added new chapter Subsystem IP Blocks.
    • Added new section AXI Stream Bridge.
    • Added IEEE 1588V2 PTP chapter.
  • Added Auto-Negotiation and Link Training chapter.
    • Added ANLT for E-Tile section.
    • Added ANLT for F-Tile section.
  • Added get_hssi_profile for E-Tile section.
  • Updated get_hssi_profile for F-Tile
  • Added set_hssi_profile for E-Tile section.
  • Updated set_hssi_profile for F-Tile.
  • Updated read_MAC_statistic table in Subsystem Abstraction Layer(SAL) Commands.
  • Updated get_mtu section.
  • Updated get_csr for E-Tile section.
  • Added Register Description for E-tile in Ncsi_get_link_status section.
  • Added a table signals mapping between 100G and 25G AXI-ST on the same interface in Dynamic Reconfiguration Extension Subsystem.
  • Updated F-Tile Address Maps section.
  • Updated E-Tile supported Example Design Variants table in Ethernet SS IP Design Example.
  • Added Steps to generate routing delay for F-Tile section in Running the Hardware Tests.
  • Added a new topic Clock Connections for SyncE Operation on F-Tile in Recommended Clock Connections.
  • Splitted F-Tile Register Map for Port Enabled with Ethernet Protocol into two tables in F-Tile Address Maps:
    • F-Tile Register Map for Port Enabled with Ethernet Protocol Port Enabled with Ethernet Protocol
    • F-Tile Register Map for per-channel Transceiver Reconfiguration Interface
  • Removed the DR support from the table F-Tile Support Example Design Variants in Ethernet SS IP Example Design.
2023.04.14 23.1
  • Updated instances of Transceiver Subsystem IP name to Ethernet Subsystem
  • Updated Introduction section with additional data rates and version.
  • Updated Ethernet Subsystem Intel FPGA IP Features table in Supported Features section.
  • Updated version to 23.1 in Getting Started section.
  • Updated Feature Description section with additional ports details.
  • Updated Supported Features section with additional ports details.
  • Updated Supported Ethernet Protocols table in Supported Features section.
  • Updated Ethernet Subsystem Intel FPGA IP Parameters: HSSI table in Parameter Editor Parameters section.
  • Updated E-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Updated F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Added new section F-tile HSSI Port to PMA Channel Mapping.
  • Updated AXI-ST Tx Client Interface Signals and AXI-ST Rx Client Interface Signals tables in AXI-ST Client Interface.
  • Updated Serial Interface Signals table in Serial Interface section.
  • Updated Clock Signals table in Clocks section.
  • Updated Alternate Clock Connections for MAC Async Client FIFO section.
  • Updated F-tile Supported Example Design Variants table in HSSI SS IP Example Design section.
  • Added new section Supported Simulators.
  • Updated Running the Simulation Tests section.
2023.01.13 22.4
  • Updated Introduction section with additional data rates.
  • Updated Transceiver Subsystem Intel FPGA IP Features table in Supported Features section.
  • Updated version to 22.4 in Getting Started section.
  • Updated Supported Ethernet Protocols table in Supported Features section.
  • Updated Transceiver Subsystem Intel FPGA IP Parameters: HSSI table and F-Tile Transceiver Subsystem Intel FPGA IP Parameters: HSSI Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Updated AXI-ST Tx Client Interface Signals table and AXI-ST Rx Client Interface Signals table in AXI-ST Client Interface section.
  • Updated Flow Control Signals table in Flow Control section.
  • Updated Serial Interface Signals table in Serial Interface section.
  • Updated Clocks Signals table in Clocks section.
  • Updated Value After Reset in Device Feature Header Hi section.
  • Updated Byte Offset information in the following sections:
    • Version
    • Feature List
    • Interface Attribute Port X Parameters
    • HSSI Command/Status
    • HSSI Read Data
    • HSSI Write Data
    • HSSI Ethernet Port X Status
  • Added F-tile ANLT Port Register Map and F-tile PTP Tile Adapter Register Map sections under Register Descriptions section.
2022.11.01 22.3 Initial release.