Ethernet Subsystem Intel® FPGA IP User Guide

Download PDF
ID 773413
Date 8/29/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide

7.3. F-Tile Address Maps

The following table provides a summary of the subsystem's register map, which includes the IP register map and an optional placeholder. Note that an address offset is assigned even for optional block(s).
Table 47.  F-Tile Register Map for Port Enabled with Ethernet Protocol
Base Address Block End Address
Subsystem
0x000_0000 Subsystem CSR 0x000_FFFF
0x001_0000 ANLT 0x0001_4FFF
0x002_0000 PTP Tile Adapter 0x0005_FFFF
  Port 0 (Quad 0 FGT 0, Port 00)
0x020_0000 EHIP – Ethernet Reconfiguration 0x020_FFFF
0x026_1000 PTP Packet Classifier 0x026_11FF
  Port 1 (Quad 0 FGT 1)
0x040_0000

EHIP – Ethernet Reconfiguration

 0x040_FFFF
0x046_1000 PTP Packet Classifier 0x046_11FF
  Port 2 (Quad 0 FGT 2)
0x060_0000 EHIP – Ethernet Reconfiguration 0x060_FFFF
0x066_1000 PTP Packet Classifier 0x066_11FF
  Port 3 (Quad 0 FGT 3)
0x080_0000 EHIP – Ethernet Reconfiguration 0x080_FFFF
0x086_1000 PTP Packet Classifier 0x086_11FF
  Port 4 (Quad 1 FGT 0)
0x0A0_0000 EHIP – Ethernet Reconfiguration 0x0A0_FFFF
0x0A6_1000 PTP Packet Classifier 0x0A6_11FF
  Port 5 (Quad 1 FGT 1)
0x0C0_0000 EHIP – Ethernet Reconfiguration 0x0C0_FFFF
0x0C6_1000 PTP Packet Classifier 0x0C6_11FF
  Port 6 (Quad 1 FGT 2)
0x0E0_0000 EHIP – Ethernet Reconfiguration 0x0E0_FFFF
0x0E6_1000 PTP Packet Classifier 0x0E6_11FF
  Port 7 (Quad 1 FGT 3)
0x100_0000 EHIP – Ethernet Reconfiguration 0x100_FFFF
0x106_1000 PTP Packet Classifier 0x106_11FF
  Port 8 (Quad 2 FGT 0)
0x120_0000 EHIP – Ethernet Reconfiguration 0x120_FFFF
0x126_1000 PTP Packet Classifier 0x126_11FF
  Port 9 (Quad 2 FGT 1)
0x140_0000 EHIP – Ethernet Reconfiguration 0x140_FFFF
0x146_1000 PTP Packet Classifier 0x146_11FF
  Port 10 (Quad 2 FGT 2)
0x160_0000 EHIP – Ethernet Reconfiguration 0x160_FFFF
0x166_1000 PTP Packet Classifier 0x166_11FF
  Port 11 (Quad 2 FGT 3)
0x180_0000 EHIP – Ethernet Reconfiguration 0x180_FFFF
0x186_1000 PTP Packet Classifier 0x186_11FF
  Port 12 (Quad 3 FGT 0)
0x1A0_0000 EHIP – Ethernet Reconfiguration 0x1A0_FFFF
0x1A6_1000 PTP Packet Classifier 0x1A6_11FF
  Port 13 (Quad 3 FGT 1)
0x1C0_0000 EHIP – Ethernet Reconfiguration 0x1C0_FFFF
0x1C6_1000 PTP Packet Classifier 0x1C6_110FF
  Port 14 (Quad 3 FGT 2)
0x1E0_0000 EHIP – Ethernet Reconfiguration 0x1E0_FFFF
0x1E6_1000 PTP Packet Classifier 0x1E6_11FF
  Port 15 (Quad 3 FGT 3)
0x200_0000 EHIP – Ethernet Reconfiguration 0x200_FFFF
0x206_1000 PTP Packet Classifier 0x206_11FF
  Port 16 ( FHT 0)
0x220_0000 EHIP – Ethernet Reconfiguration 0x220_FFFF
0x226_1000 PTP Packet Classifier 0x226_11FF
  Port 17 ( FHT 1)
0x240_0000 EHIP – Ethernet Reconfiguration 0x240_FFFF
0x246_1000 PTP Packet Classifier 0x246_11FF
  Port 18 ( FHT 2)
0x260_0000 EHIP – Ethernet Reconfiguration 0x260_FFFF
0x266_1000 PTP Packet Classifier 0x266_11FF
  Port 19 ( FHT 3)
0x280_0000 EHIP – Ethernet Reconfiguration 0x280_FFFF
0x286_1000 PTP Packet Classifier 0x286_11FF
Table 48.  F-Tile Register Map for per-channel Transceiver Reconfiguration Interface
Base Address Block End Address
  Channel 0 (Quad 0 FGT 0, Port 00)
0x030_0000 PHY – XCVR Reconfiguration 0x03F_FFFF
  Channel 1 (Quad 0 FGT 1)
0x050_0000 PHY – XCVR Reconfiguration 0x05F_FFFF
  Channel 2 (Quad 0 FGT 2)
0x070_0000 PHY – XCVR Reconfiguration 0x07F_FFFF
  Channel 3 (Quad 0 FGT 3)
0x090_0000 PHY – XCVR Reconfiguration 0x09F_FFFF
  Channel 4 (Quad 1 FGT 0)
0x0B0_0000 PHY – XCVR Reconfiguration 0x0BF_FFFF
  Channel 5 (Quad 1 FGT 1)
0x0D0_0000 PHY – XCVR Reconfiguration 0x0DF_FFFF
  Channel 6 (Quad 1 FGT 2)
0x0F0_0000 PHY – XCVR Reconfiguration 0x0FF_FFFF
  Channel 7 (Quad 1 FGT 3)
0x110_0000 PHY – XCVR Reconfiguration 0x11F_FFFF
  Channel 8 (Quad 2 FGT 0)
0x130_0000 PHY – XCVR Reconfiguration 0x13F_FFFF
  Channel 9 (Quad 2 FGT 1)
0x150_0000 PHY – XCVR Reconfiguration 0x15F_FFFF
  Channel 10 (Quad 2 FGT 2)
0x170_0000 PHY – XCVR Reconfiguration 0x17F_FFFF
  Channel 11 (Quad 2 FGT 3)
0x190_0000 PHY – XCVR Reconfiguration 0x19F_FFFF
  Channel 12 (Quad 3 FGT 0)
0x1B0_0000 PHY – XCVR Reconfiguration 0x1BF_FFFF
  Channel 13 (Quad 3 FGT 1)
0x1D0_0000 PHY – XCVR Reconfiguration 0x1DF_FFFF
  Channel 14 (Quad 3 FGT 2)
0x1F0_0000 PHY – XCVR Reconfiguration 0x1FF_FFFF
  Channel 15 (Quad 3 FGT 3)
0x210_0000 PHY – XCVR Reconfiguration 0x21F_FFFF
  Channel 16 ( FHT 0)
0x230_0000 PHY – XCVR Reconfiguration 0x23F_FFFF
  Channel 17 ( FHT 1)
0x250_0000 PHY – XCVR Reconfiguration 0x25F_FFFF
  Channel 18 ( FHT 2)
0x270_0000 PHY – XCVR Reconfiguration 0x27F_FFFF
  Channel 19 ( FHT 3)
0x290_0000 PHY – XCVR Reconfiguration 0x29F_FFFF
The following table shows the F-Tile Ethernet Reconfiguration Avalon Memory-Mapped address ranges.
Table 49.  F-Tile Ethernet Reconfiguration Avalon® Memory-Mapped Address Ranges
Register Type Address Range
F-Tile AIB Config 0x0000 – 0x00FC
Soft CSRs 0x0100 – 0x0FFC
EHIP Registers 0x1000 – 0x5FFC
FEC/XCVRIF Registers 0x6000 – 0x9FFC

The Ethernet Reconfiguration interface provides access to the EHIP Avalon® memory-mapped address space for the local EHIP fracture, including MAC, PCS, FEC and XCVRIF, as well as soft CSRs implemented in the FPGA fabric. The layout of this register space is described in more detail in the F-tile Hard IP for Ethernet User Guide. All addresses in this section are byte addresses, although the registers described are always accessed on 32-bit boundaries.

The EHIP and FEC/XCVRIF Registers spaces are mapped differently for different ethernet modes (10g/25g, 50g, 40g/100g, 200g, 400g) and are described in the F-tile Hard IP for Ethernet User Guide.

Table 50.  F-tile Ethernet Base Address Ranges
Ethernet Mode eth_reconfig Base Address
10g/25g 0x1000
50g 0x2000
40g/100g 0x3000
200g 0x4000
400g 0x5000

The following table shows the F-tile CSR address (Section 8 in F-Tile Ethernet Intel® FPGA Hard IP User Guide) mapping for channel 0/Quad 0 FGT 0. The CSR address mapping for different channels share the same byte offset. For example, channel 0 base address starts at 0x020_0000, and channel 8 base address is 0x120_0000. You can directly add the CSR byte offset address with base address of the channel to obtain the CSR address on particular channel. The CSR address is in byte offset, so the offset is directly added to base address without multiplication. To access this register, you must write bits 2-25 of this calculated address to the HSSI Control/Address CSR with the set_csr SAL command.

Table 51.  F-tile CSR Address
Base Address Byte Offset Descriptions Configuration
Channel 0 (Quad 0 FGT 0) -
0x020_0000 (EHIP – Ethernet Reconfiguration) 0x0000 – 0x00FC F-Tile AIB Config -
0x0100 – 0x0FFC Soft CSRs
0x1000 (10GE/25GE) 0x000-0x07C PCS Configuration
0x080-0x1FC PCS Status
0x200-0x7FC MAC/PTP Configuration
0x800-0xFFC MAC/PTP Statistics
0x2000 (50GE) Same as above Same as above
0x3000 (40GE/100GE) Same as above Same as above
0x4000 (200GE) Same as above Same as above
0x5000 (400GE) Same as above Same as above
0x020_0000 (FEC/XCVR – Ethernet Reconfiguration) eth_reconfig Base Address Offset Address FEC/XCVRIF Lane Segment
0x6000 (25g) 0x000 - 0x0BC (Transceiver Interface Control ) segment 0
0x0C0 - 0x0FC (FEC Configuration )
0x100 - 0x13C (Transceiver Status)
0x140 - 0x1FC (FEC Status )
0x6200 (50g) Same as above segment 0
0x6400 (50g) Same as above segment 1
0x6600 (100g) Same as above segment 0
0x6800 (100g) Same as above segment 1
0x6A00 (100g) Same as above segment 2
0x6C00 (100g) Same as above segment 3
0x6E00 (200g) Same as above segment 0
0x7000 (200g) Same as above segment 1
0x7200 (200g) Same as above segment 2
0x7400 (200g) Same as above segment 3
0x7600 (200g) Same as above segment 4
0x7800 (200g) Same as above segment 5
0x7A00 (200g) Same as above segment 6
0x7C00 (200g) Same as above segment 7
0x7E00 (400g) Same as above segment 0
0x8000 (400g) Same as above segment 1
0x8200 (400g) Same as above segment 2
0x8400 (400g) Same as above segment 3
0x8600 (400g) Same as above segment 4
0x8800 (400g) Same as above segment 5
0x8A00 (400g) Same as above segment 6
0x8C00 (400g) Same as above segment 7
0x8E00 (400g) Same as above segment 8
0x9000 (400g) Same as above segment 9
0x9200 (400g) Same as above segment 10
0x9400 (400g) Same as above segment 11
0x9600 (400g) Same as above segment 12
0x9800 (400g) Same as above segment 13
0x9A00 (400g) Same as above segment 14
0x9C00 (400g) Same as above segment 15
0x020_A000 (Reserved) - Reserved -
0x021_1000 (PTP Packet Classifier) - PTP Packet Classifier -
0x024_0000 (PHY – XCVR Reconfiguration) - PHY – XCVR Reconfiguration -

The following example shows CSR access decoding.

Assuming you would like to access Tx MAC Link Fault Config register (For details, refer to F-tile Hard IP for Ethernet Register Map) for Agilex F-tile channel 8.

Tx MAC Link Fault Config register byte offset = 0x1200

F-tile transceiver channel 8 base address = 0x1200000

AXI-Lite CSR read request address = 0x405*4 + 0x1200000 = 0x1201014 (byte addressing)

This request will be decoded and routed to Ethernet Reconfiguration interface for processing.

Table 52.  Ethernet Reconfiguration Interface Register Base Addresses (F-tile)
Ethernet Mode FEC/XCVRIF Lane Segment eth_reconfig Base Address
25g s0 0x6000
50g s0 0x6200
s1 0x6400
100g s0 0x6600
s1 0x6800
s2 0x6A00
s3 0x6C00
200g s0 0x6E00
s1 0x7000
s2 0x7200
s3 0x7400
s4 0x7600
s5 0x7800
s6 0x7A00
s7 0x7C00
400g s0 0x7E00
s1 0x8000
s2 0x8200
s3 0x8400
s4 0x8600
s5 0x8800
s6 0x8A00
s7 0x8C00
s8 0x8E00
s9 0x9000
s10 0x9200
s11 0x9400
s12 0x9600
s13 0x9800
s14 0x9A00
s15 0x9C00
Related Information
Level Two Title