External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Intel Agilex® 7 M-Series EMIF IP 2.7. Compiling the Intel Agilex® 7 M-Series EMIF Design Example
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4 2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type 2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel Agilex® 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for a x32 + ECC interface Example: Swizzling for a x32 + ECC interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

2.3.4. Example: Swizzling for a x32 + ECC interface

Example: Swizzling for a x32 + ECC interface

Table 10.  
Scheme BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
DDR4_AC_TOP DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC0 sDQ[0]
DQS group number in byte swizzling notation 3 2 1 0 AC1 AC2 AC0 ECC
After Byte Swizzling 3 2 0 1 X X X ECC

In this example, BL7 cannot be swapped with other used DQS group. It is used as follows:

  • RUSER/WUSER Lane in x40 configuration
  • ECC Lane in x32 + ECC configuration

This example illustrates swizzling DQS group 1 (BL3) with DQS group 0 (BL2). To achieve this swizzling, enter the following BYTE_SWIZZLE_CH0 specification in the USER Extra Parameters:

BYTE_SWIZZLE_CH0= 3,2,0,1,X,X,X,ECC

In DDR4 x32 + ECC configuration, the highest index DQS group is used as ECC lane. We use PIN_SWIZZLE_CH0_ECC for swizzle the DQ pins within the ECC lane in this case. Note that the valid value for pin swizzling specification in the ECC lane is always 0-7 only.

Table 11.  Example of DQ pin swizzling in ECC lane for a DDR4 x32 + ECC interface
Lane Pin Index Default Placement After Swizzling
BL7 95 MEM_DQ[39] MEM_DQ[36]
94 MEM_DQ[38] MEM_DQ[37]
93 MEM_DQ[37] MEM_DQ[38]
92 MEM_DQ[36] MEM_DQ[39]
91    
90 MEM_DM_N[4] MEM_DM_N[4]
89 MEM_DM_C[4] MEM_DM_C[4]
88 MEM_DM_T[4] MEM_DM_T[4]
87 MEM_DQ[35] MEM_DQ[34]
86 MEM_DQ[34] MEM_DQ[35]
85 MEM_DQ[33] MEM_DQ[32]
84 MEM_DQ[32] MEM_DQ[33]

To achieve the pin swizzling shown in the above table, enter the following BYTE_SWIZZLE_CH0 specification in User Extra Parameters:

PIN_SWIZZLE_CH0_ECC=1,0,3,2,7,6,5,4;
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