External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Intel Agilex® 7 M-Series EMIF IP 2.7. Compiling the Intel Agilex® 7 M-Series EMIF Design Example
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4 2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type 2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel Agilex® 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for a x32 + ECC interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface

Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface

This example uses the lane placement of the following table, using a memory device of x8 width.

Table 5.  Lane Placement for a x32 DDR4 Interface
Lane Number BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Default placement DQ[0] AC0 AC1 AC2 DQ[1] DQ[2] DQ[3] GPIO
Table 6.  Example of Swizzling DQ pin in BL0 ( DQS group 0)
Lane Pin Index DDR4 x32 (Default Placement) After Swizzling / Swapping
BL0 11 MEM_DQ[7] MEM_DQ[6]
10 MEM_DQ[6] MEM_DQ[5]
9 MEM_DQ[5] MEM_DQ[7]
8 MEM_DQ[4] MEM_DQ[4]
7    
6 MEM_DM_N[0] MEM_DM_N[0]
5 MEM_DQS_C[0] MEM_DQS_C[0]
4 MEM_DQS_T[0] MEM_DQS_T[0]
3 MEM_DQ[3] MEM_DQ[0]
2 MEM_DQ[2] MEM_DQ[2]
1 MEM_DQ[1] MEM_DQ[1]
0 MEM_DQ[0] MEM_DQ[3]

To achieve this swizzling in DQS group 0, you must enter PIN_SWIZZLE_CH0_DQS0=3,1,2,0,4,7,5,6; in the User Extra Parameters field of the Additional Parameters tab in the Advanced Parameters section of the General IP Parameters tab in the External Memory Interfaces IP parameter editor.

Figure 23. Entering a PIN_SWIZZLE Specification
Table 7.  Example of Swizzling DQ pin in BL5 ( DQS group 2)
Lane Pin Index DDR4 x32 (from table) After Swizzling / Swapping
BL5 71 MEM_DQ[23] MEM_DQ[17]
70 MEM_DQ[22] MEM_DQ[22]
69 MEM_DQ[21] MEM_DQ[21]
68 MEM_DQ[20] MEM_DQ[20]
67    
66 MEM_DM_N[2] MEM_DM_N[2]
65 MEM_DQS_C[2] MEM_DQS_C[2]
64 MEM_DQS_T[2] MEM_DQS_T[2]
63 MEM_DQ[19] MEM_DQ[19]
62 MEM_DQ[18] MEM_DQ[18]
61 MEM_DQ[17] MEM_DQ[23]
60 MEM_DQ[16] MEM_DQ[16]

To achieve this swizzling in DQS Group 2, you must enter PIN_SWIZZLE_CH0_DQS2=16,23,18,19,20,21,22,17; in the User Extra Parameters field of the Additional Parameters tab in the Advanced Parameters section of the General IP Parameters tab in the External Memory Interfaces IP parameter editor.

Figure 24. Entering a PIN_SWIZZLE Specification

You can enter multiple specifications in the User Extra Parameters field, each separated by a comma.

Figure 25. Entering Multiple PIN_SWIZZLE Specifications
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