External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Intel Agilex® 7 M-Series EMIF IP 2.7. Compiling the Intel Agilex® 7 M-Series EMIF Design Example
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4 2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type 2.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR42.1.1.3.12.1.1.3.32.1.1.3.5. Generating a Custom Memory Preset File for DDR4
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel Agilex® 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for a x32 + ECC interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

2.3. Configuring DQ Pin Swizzling

It is important to strictly follow the pin placement for a given memory topology when assigning pin locations for your EMIF IP.

Do not change the location for the EMIF pin using a .qsf assignment or the pin planner if you need to swap the DQ pins within a DQS group or the DQS group to simplify board design. For example, if you implement a x32 DDR4 interface, the EMIF pin location must adhere to the x32 column in the DDR4 Pin Placement table in the Product Architecture chapter of the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide. There is no flexibility to swap the address command pin location.

The following tables summarize the parameters for pin swizzling and byte swizzling, respectively.

Table 3.  User Extra Parameters for Swizzling the DQ Pin
Parameter Description
PIN_SWIZZLE_CH<m>_DQS<n>

Used for swizzling DQ pin within DQS group <n> for channel <m>.

m=0 only for DDR4.
PIN_SWIZZLE_CH<m>_ECC Used for swizzling DQ pin within the following lane:
  • ECC (When side-band ECC is enabled)
  • RUSER/WUSER lane (when Extra DQ Byte Lane is enabled)
m=0 only for DDR4
PIN_SWIZZLE_PRI_DQS<n> Used for swizzling DQ pin within DQS group <n> in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
PIN_SWIZZLE_SEC_DQS<n> Used for swizzling DQ pin within DQS group <n> in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
PIN_SWIZZLE_PRI_ECC Used for swizzling DQ pin within the ECC lane or RUSER/WUSER lane (when the Extra DQ Byte Lane is enabled), if this lane is implemented in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
PIN_SWIZZLE_SEC_ECC Used for swizzling DQ pin within the ECC lane or RUSER/WUSER lane (when the Extra DQ Byte Lane is enabled), if this lane is implemented in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.

For device widths of x4 and x8, you can swizzle each DQ pin within its DQS group. For device widths of x16, you can swizzle each DQ pin within the lower byte and upper byte respectively. You cannot swizzle DQ pin for the lower byte to upper byte and vice versa.

Table 4.  User Extra Parameters for Byte Swizzling
Parameter Description
BYTE_SWIZZLE_CH<n>

Used for swizzling DQS group for CH<n> of the interface.

m=0 for DDR4.
BYTE_SWIZZLE_PRI Used for swizzling DQS group in the primary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.
BYTE_SWIZZLE_SEC Used for swizzling DQS group in the secondary IO96 bank. This parameter is only applicable for lockstep configuration implemented with 2 adjacent IO96 banks.

Section Content
Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface
Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width
Combining Pin and Byte Swizzling
Example: Swizzling for a x32 + ECC interface
Example: Byte Swizzling for Lockstep Configuration

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