Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 4/17/2023
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Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

4.1.1. Port Descriptions

Table 1.  Dual-Port RAM Parameterizable Macros Port Descriptions
Port Type Required Description
clock0 Input Yes The following describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to clock0 port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your read clock to clock0 port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock.
  • Input Output: Connect your input clock to clock0 port. All registered input ports are synchronized by the input clock.
  • Independent clock: Connect your port A clock to clock0 port. All registered input and output ports of port A are synchronized by the port A clock.
clock1 Input Optional The following describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes:
  • Single clock: Not applicable. All registered ports are synchronized by clock1 port.
  • Read/Write: Connect your read clock to clock1 port. All registered ports related to read operation, such as address_b port and rden_b port are synchronized by the read clock.
  • Input Output: Connect your output clock to clock1 port. All the registered output ports are synchronized by the output clock.
  • Independent clock: Connect your port B clock to clock1 port. All registered input and output ports of port B are synchronized by the port B clock.
clocken0 Input Optional Clock enable input for clock0 port.
clocken1 Input Optional Clock enable input for clock1 port.
aclr0 Input Optional Asynchronous clear port. Clears the registered input and output ports clocked by clock0.
aclr1 Input Optional Asynchronous clear port. Clears the registered input and output ports clocked by clock1.
sclr Input Optional Synchronous clear port. Clears the registered data output ports.
data_a Input Yes Data input port at port A.
address_a Input Yes Address port at port A.
wren_a Input Optional (Always pull low if not connected) Write enable port at Port A.
byteena_a Input Optional Byte enable port at Port A to mask the data_a port so that only specific bits of the data are written to the memory.
address_b Input Optional Address port at port B.
rden_b Input Optional Read enable port for port B.
q_b Output Yes Data output port at port B. The width of q_b port must be equal to the width of data_b port.
addressstall_a Input Optional Address clock enable input to hold the previous address of address_a port for provided that the addressstall_a port is high.
addressstall_b Input Optional Address clock enable input to hold the previous address of address_b port for provided that the addressstall_b port is high.
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