Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 4/17/2023
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Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

5.2.2. Parameters

Table 8.  SYNC_FIFO Parameterizable Macros Parameters
Parameter Allowed Values Description
DATA_WIDTH 8 Specifies the width of the data and q ports.
ADDR_WIDTH 11 Specifies the width of the usedw port.
ENABLE_ACLR

ON

OFF

Specifies whether to set ENABLE_ACLR parameter ON or OFF. Asynchronous clear choice for data output of FIFO.
ENABLE_SCLR

ON

OFF

Specifies whether to ENABLE_SCLR parameter ON or OFF. Synchronous clear choice for data output of FIFO.
ENABLE_SHOWAHEAD

ON

OFF

Specifies whether the FIFO is in normal mode (OFF) or show-ahead mode (ON).

For normal mode, the FIFO treats the rdreq port as a normal read request that only performs read operation when the port is asserted.

For show-ahead mode, FIFO treats the rdreq port as a read-acknowledge that automatically outputs the first word of valid data in the FIFO (when the empty port is low) without asserting the rdreq signal. Asserting the rdreq signal causes the FIFO IP to output the next data word, if available.

Setting ON to this parameter may reduce performance.

MAXIMUM_DEPTH 2048 Maximum depth. You can set the preferred maximum depth with MAXIMUM_DEPTH=<depth>. The value assigned must comply with this equation: 2^ADDR_WIDTH
OVERFLOW_CHECKING

ON

OFF

Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO is full. The values are ON or OFF. If omitted, the default is ON.
UNDERFLOW_CHECKING

ON

OFF

Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq port when the FIFO is empty. The values are ON or OFF. If omitted, the default is ON.

Note that reading from an empty SCFIFO gives unpredictable results.
RAM_BLOCK_TYPE

AUTO

MLAB

M20K

Specifies the target device’s Memory Block to be used: "Auto", "MLAB", "M20K".
ADD_RAM_OUTPUT_REGISTER

ON

OFF

Specifies whether to register the q output. The values are ON and OFF. The default value is OFF.
ALMOST_FULL_VALUE 1 Sets the threshold value for the almost_full port. When the number of words stored in the FIFO is greater than or equal to this value, the almost_full port is asserted.
ALMOST_EMPTY_VALUE 1 Sets the threshold value for the almost_empty port. When the number of words stored in the FIFO is lesser than this value, the almost_empty port is asserted.
ALLOW_RWCYCLE_WHEN_FULL

ON

OFF

Allows you to combine read and write cycles to an already full SCFIFO, so that it remains full. The values are ON and OFF. The default is OFF. Use this parameter only when the OVERFLOW_CHECKING parameter is set to ON.
BYTE_SIZE

5

8

9

10

Specifies the size of the byte for byte-enable mode
BYTE_EN_WIDTH 1

Width of the byte-enable bus at Port A.

This width should be equal to DATA_WIDTH divided by BYTE_SIZE.

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