5.1.3. Instantiation Template
ASYNC_FIFO VHDL Instantiation Template
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
-- Instantiating ASYNC_FIFO
<instance_name> : ASYNC_FIFO
generic map (
DATA_WIDTH_A => 8,
ADDR_WIDTH_A => 11,
DATA_WIDTH_B => 8,
ADDR_WIDTH_B => 11,
RDSYNC_DELAYPIPE => 2,
WRSYNC_DELAYPIPE => 2,
ENABLE_SHOWAHEAD => "OFF",
UNDERFLOW_CHECKING => "ON",
OVERFLOW_CHECKING => "ON",
ADD_USEDW_MSB_BIT => "OFF",
WRITE_ACLR_SYNCH => "OFF",
READ_ACLR_SYNCH => "OFF",
ADD_RAM_OUTPUT_REGISTER => "OFF",
RAM_BLOCK_TYPE => "M20K",
MAXIMUM_DEPTH => 2048,
BYTE_EN_WIDTH => 1,
BYTE_SIZE => 8
)
port map (
data => _connected_to_data_, -- input, width = DATA_WIDTH_A
rdclk => _connected_to_rdclk_, -- input, width = 1
wrclk => _connected_to_wrclk_, -- input, width = 1
aclr => _connected_to_aclr_, -- input, width = 1
rdreq => _connected_to_rdreq_, -- input, width = 1
wrreq => _connected_to_wrreq_, -- input, width = 1
byteena => _connected_to_byteena_, -- input, width = BYTE_EN_WIDTH
rdfull => _connected_to_rdfull_, -- output, width = 1
wrfull => _connected_to_wrfull_, -- output, width = 1
rdempty => _connected_to_rdempty_, -- output, width = 1
wrempty => _connected_to_wrempty_, -- output, width = 1
rdusedw => _connected_to_rdusedw_, -- output, width = ADDR_WIDTH_B
wrusedw => _connected_to_wrusedw_, -- output, width = ADDR_WIDTH_A
q => _connected_to_q_ -- output, width = DATA_WIDTH_B
}; ASYNC_FIFO Verilog Instantiation Template
//Quartus Prime Parameterizable Macro Template
//ASYNC FIFO
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/async_fifo.v
async_fifo #(
.DATA_WIDTH_A (8),
.ADDR_WIDTH_A (11),
.DATA_WIDTH_B (8),
.ADDR_WIDTH_B (11),
.RDSYNC_DELAYPIPE (2),
.WRSYNC_DELAYPIPE (2),
.ENABLE_SHOWAHEAD ("OFF"),
.UNDERFLOW_CHECKING ("ON"),
.OVERFLOW_CHECKING ("ON"),
.ADD_USEDW_MSB_BIT ("OFF"),
.WRITE_ACLR_SYNCH ("OFF"),
.READ_ACLR_SYNCH ("OFF"),
.ADD_RAM_OUTPUT_REGISTER ("OFF"),
.RAM_BLOCK_TYPE ("M20K"),
.MAXIMUM_DEPTH (2048),
.BYTE_EN_WIDTH (1),
.BYTE_SIZE (8)
) <instance_name> (
.data (_connected_to_data_),
.rdclk (_connected_to_rdclk_),
.wrclk (_connected_to_wrclk_),
.aclr (_connected_to_aclr_),
.rdreq (_connected_to_rdreq_),
.wrreq (_connected_to_wrreq_),
.byteena (_connected_to_byteena_),
.rdfull (_connected_to_rdfull_),
.wrfull (_connected_to_wrfull_),
.rdempty (_connected_to_rdempty_),
.wrempty (_connected_to_wrempty_),
.rdusedw (_connected_to_rdusedw_),
.wrusedw (_connected_to_wrusedw_),
.q (_connected_to_q_)
);