AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex® F-Tile Devices

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ID 763505
Date 1/10/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and DAC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Summary 1.9. Document Revision History for AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-Tile Devices
1.4. Interoperability Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer (TL)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices

1.3. System Description

The following system-level diagram shows how the different modules are connected in this design.

Figure 2. System Diagram

In this setup, for example L = 8, M = 4, and F = 1, the data rates of the transceiver lanes are 24.75 Gbps.

The Si5332 OUT1 generates 100 MHz clock to mgmt_clk. Si5345-D-EVB generates two clock frequencies, 375 MHz and 100 MHz. The 375 MHz is supplied to the embedded multiplexer in the Intel® Agilex™ I-Series F-tile demo board through the J19 SMA port. The output clock of the embedded multiplexer drives the F-tile transceiver reference clock (refclk_xcvr) and JESD204C Intel® FPGA IP core PLL reference clock (refclk_core). 100 MHz from Si5345-D-EVB is connected to the HMC7044 programmable clock generator present in the AD9081 EVM as the clock input (EXT_HMCREF).

The HCM7044 generates a periodic SYSREF signal of 11.71875 MHz through the FMC connector.

The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the transmitter path is used.

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