AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex® F-Tile Devices

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ID 763505
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and DAC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Summary 1.9. Document Revision History for AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-Tile Devices
1.4. Interoperability Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer (TL)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices

1.5. JESD204C Intel® FPGA IP and DAC Configurations

The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device. The transceiver data rate, sampling clock, and other JESD204C parameters comply with the AD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configuration.

Global setting for all configuration:
  • E = 1
  • CF = 0
  • CS = 0
  • Subclass = 1
  • FCLK_MULP = 1
  • WIDTH_MULP = 8
  • SH_CONFIG = CRC-12
  • FPGA Management Clock (MHz) = 100
Table 3.  Parameter Configuration
No. L M F S HD E N NP DAC Sampling Clock (MHz) FPGA Device Clock (MHz) Coarse Inter-

polation

 Fine Inter-

polation

 Lane Rate (Gbps) Data Pattern
1 8 4 1 1 0 1 16 16 6000 375 2 1 24.75 PRBS

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