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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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2.3. Functional Description
The F-Tile 25G Ethernet single-channel design example consists of MAC+PCS+PMA core variant. The following block diagrams show the design components and the top-level signals of the MAC+PCS+PMA core variant in the F-Tile 25G Ethernet design example.
Figure 5. Block Diagram—F-Tile 25G Ethernet Single-Channel Design Example (MAC+PCS+PMA Core Variant)