Visible to Intel only — GUID: dfk1697527414057
Ixiasoft
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
Visible to Intel only — GUID: dfk1697527414057
Ixiasoft
3.3.1. Design Components
Component | Description |
---|---|
F-Tile 25G Ethernet Intel FPGA IP | Consists of MAC, PCS, and Transceiver PHY, with the following configuration:
|
SYS PLL | Generates reference and system clocks for the 10G/25G transceivers. |
Client logic | Consists of:
|
Source and Probe | Source and probe signals, including system reset input signal, which you can use for debugging. |
Dynamic reconfiguration controller | Dynamic reconfiguration controller is generated when you generate the single-channel design example with dynamic reconfiguration. |