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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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2.2. Hardware and Software Requirements
Intel® uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime Pro Edition software
- Siemens* EDA QuestaSim* , Synopsys* VCS* , and Cadence Xcelium* simulator
- Intel Agilex® 7 I-series Transceiver-SoC Development Kit (AGIB027R31B1E2V) for hardware testing