Visible to Intel only — GUID: vye1662364141644
Ixiasoft
Visible to Intel only — GUID: vye1662364141644
Ixiasoft
2.3.1. Design Components
Component | Description |
---|---|
F-Tile 25G Ethernet Intel FPGA IP | Consists of MAC, PCS, and Transceiver PHY, with the following configuration:
For the design example with the RS-FEC feature, the following additional parameter is configured:
|
F-Tile Reference and System PLL Clocks Intel® FPGA IP | The F-Tile Reference and System PLL Clocks Intel® FPGA IP parameter editor settings align with the requirements of the F-Tile 25G Ethernet Intel FPGA IP. If you generate the design example using Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own design example, you must manually instantiate this IP and connect all I/O ports. For information about this IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. |
Client logic | Consists of:
|
Source and Probe | Source and probe signals, including system reset input signal, which you can use for debugging. |