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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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3.4.1. Testbench
Figure 9. Block Diagram of the F-Tile 25G Ethernet Single-Channel Design Example with Dynamic Reconfiguration Simulation Testbench
Component | Description |
---|---|
Device under test (DUT) | The F-Tile 25G Ethernet Intel FPGA IP core. |
Ethernet Packet Generator and Packet Monitor |
|
SYS PLL | Generates clock for the Intel Agilex® 7 I-Series SoC 25G transceiver which is wrapped in the F-Tile 25G Ethernet Intel FPGA IP. |
Dynamic reconfiguration controller | If you generate the single-channel design example with dynamic reconfiguration, this IP is automatically instantiated. |