F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 11/29/2023
Public

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6. Reset

Control and Status registers control three parallel soft resets. These soft resets are not self-clearing. Software clears them by writing to the appropriate register. Asserting the external hard reset csr_rst_n returns Control and Status registers to their original values.
Figure 19. Conceptual Overview of Reset LogicThe three hard resets are top-level ports. The soft resets are internal signals which are outputs of the hard IP eth_reset register. Software writes the appropriate bit of the eth_reset to assert a soft reset.
The general reset signals reset the following functions:
  • i_tx_rst_n: Resets the TX datapath, including TX MAC, TX PCS, TX transceiver, and TX EMIB adapters.
  • i_rx_rst_n: Resets the RX datapath, including RX MAC, RX PCS, RX transceiver, and RX EMIB adapters.
  • i_rst_n: Resets TX and RX PCS, transceiver, and EMIB adapters.
  • csr_rst_n: Resets TX and RX MAC CSR registers.
  • reconfig_reset: Resets the ethernet and transceiver reconfiguration clock domain, including the soft CSR registers and Avalon® memory-mapped interface.
  • reset_status: Resets the Avalon® memory-mapped management interface.
Table 11.  Reset Signals FunctionsA tick (√) represents the block that is reset by the specified reset signal.
Reset Signal Datapath PHY Statistics CSR
TX MAC RX MAC TX PCS RX PCS TX RX TX MAC RX MAC MAC PHY
Port Reset
i_rst_n
i_tx_rst_n    
i_rx_rst_n
csr_rst_n
reconfig_reset
Register Reset
eio_sys_rst
soft_tx_rst
soft_rx_rst