F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 11/29/2023
Public

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7.7. Miscellaneous Status and Debug Signals

The miscellaneous status and debug signals are asynchronous.
Table 19.  Miscellaneous Status and Debug Signals

Signal

Direction

Description

tx_lanes_stable Output Active-high asynchronous status signal for the TX datapath.
  • Asserts when the TX datapath is ready to send data.
  • Deasserts when i_tx_rst_n/i_rst_n signal asserts.
rx_block_lock Output

If you turn off Enable RS-FEC in the parameter editor, this signal is asserted when the IP completes 66-bit block boundary alignment on all PCS lanes.

If you turn on Enable RS-FEC in the parameter editor, this signal is asserted when the IP completes the codeword alignment on all FEC lanes.

rx_pcs_ready Output Active-high asynchronous status signal for the RX datapath.
  • Asserts when the RX datapath is ready to receive data.
  • Deasserts when i_rx_rst_n/i_rst_n signal asserts or during the auto-negotiation and link training operation.
local_fault_status Output Asserted when the RX MAC detects a local fault. This signal is available if you turn on Enable link fault generation in the parameter editor.
remote_fault_status Output Asserted when the RX MAC detects a remote fault. This signal is available if you turn on Enable link fault generation in the parameter editor.
unidirectional_en Output Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.
link_fault_gen_en Output Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.
o_tx_pll_locked Output Indicates that the TX SERDES PLLs are locked.
o_cdr_lock Output Indicates that the recovered clocks are locked to data.
o_rx_hi_ber Output Asserted when the RX PCS is in a HI BER state according to Figure 82-15 in the IEEE 802.3-2015 Standard.