F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 11/29/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.5.3. Placement Settings for the F-Tile 25G Ethernet Intel FPGA IP Core

The Quartus Prime software provides the options to specify design partitions and Logic Lock (Standard) or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.

The appropriate floorplan is always design-specific, and depends on your design.