F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 11/29/2023
Public

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Document Table of Contents

1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.2
IP Version 2.0.0
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile 25G Ethernet Intel FPGA IP for the Intel Agilex® 7 devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the F-Tile 25G Ethernet Intel FPGA IP protocol.
Table 1.  Related Documents
Reference Description
F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Provides information about how to instantiate F-Tile 25G Ethernet Intel FPGA IP design examples using the Intel Agilex® 7 (F-Tile) devices.
F-Tile 25G Ethernet Intel FPGA IP Release Notes Lists the changes made for the F-Tile 25G Ethernet Intel FPGA IP in a particular release.
F-Tile Ethernet Intel FPGA Hard IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile Ethernet Intel FPGA Hard IP User Guide.
F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Provides information about the architecture and implementation details for the Intel Agilex® 7 F-Tile building blocks, physical (PHY) layer IP, PLLs, and clock networks.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
ALM Adaptive Logic Element
AVMM Avalon® memory-mapped interface
AVST Avalon® streaming interface
AXI ARM corporation's Advanced Extensible Interface
CRC Cyclic redundancy code
CSR Control and Status Register
EMIB Intel Embedded Silicon Bridge technology
FCQN Flow Control Queue Number
FPGA Field Programmable Gate Array
LAB Logic Array Block
MAC Media Access Control
MLAB Memory Logic Array Block
PCS Physical coding sublayer
PFC Priority-based flow control
PHY Physical layer
PLL Phase-locked loop
PMA Physical medium attachment
QN Queue Number