AN 987: Static Update Partial Reconfiguration Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

Download PDF
ID 749443
Date 10/24/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board
2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
2.1. Tutorial Requirements 2.2. Reference Design Overview 2.3. Static Update Region Overview 2.4. Download Reference Design Files 2.5. Reference Design Walkthrough 2.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial Revision History
2.5. Reference Design Walkthrough x
2.5.1. Step 1: Getting Started 2.5.2. Step 2: Create Design Partitions 2.5.3. Step 3: Allocate Placement and Routing Regions 2.5.4. Step 4: Define Personas 2.5.5. Step 5: Create Revisions 2.5.6. Step 6: Compile the Base Revision 2.5.7. Step 7: Set Up PR Implementation Revisions 2.5.8. Step 8: Change the SUPR Logic 2.5.9. Step 9: Program the Board 2.5.10. Modifying the SUPR Partition
2.5.5. Step 5: Create Revisions x
2.5.5.1. Setting the Base Revision 2.5.5.2. Creating Implementation Revisions
2.5.9. Step 9: Program the Board x
2.5.9.1. Troubleshooting PR Programming Errors
1. Answers to Top FAQs
2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1. Answers to Top FAQs

Updated for:
Intel® Quartus® Prime Design Suite 22.3

What is static update partial reconfiguration

Static Update Partial Reconfiguration

What do I need for this tutorial?

Tutorial Requirements

Where can I get the reference design?

Download Reference Design Files

How do I create an SUPR design?

Reference Design Walkthrough

What is a PR persona?

Define Personas

How do I change SUPR logic?

Change the SUPR Logic

How do I program the board?

Program the Board

What are the PR known issues and limitations?

Intel FPGA Support Forums: PR

Do you have training on PR?

Intel FPGA Technical Training Catalog

Level Two Title