AN 987: Static Update Partial Reconfiguration Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 749443
Date 10/24/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board
2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
2.1. Tutorial Requirements 2.2. Reference Design Overview 2.3. Static Update Region Overview 2.4. Download Reference Design Files 2.5. Reference Design Walkthrough 2.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial Revision History
2.5. Reference Design Walkthrough x
2.5.1. Step 1: Getting Started 2.5.2. Step 2: Create Design Partitions 2.5.3. Step 3: Allocate Placement and Routing Regions 2.5.4. Step 4: Define Personas 2.5.5. Step 5: Create Revisions 2.5.6. Step 6: Compile the Base Revision 2.5.7. Step 7: Set Up PR Implementation Revisions 2.5.8. Step 8: Change the SUPR Logic 2.5.9. Step 9: Program the Board 2.5.10. Modifying the SUPR Partition
2.5.5. Step 5: Create Revisions x
2.5.5.1. Setting the Base Revision 2.5.5.2. Creating Implementation Revisions
2.5.9. Step 9: Program the Board x
2.5.9.1. Troubleshooting PR Programming Errors
1. Answers to Top FAQs
2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board

2.5.4. Step 4: Define Personas

This reference design defines three separate personas for the single PR partition, and one SUPR persona for the SUPR region. Follow these steps to define and include these personas in your project. If using the Intel® Quartus® Prime Text Editor, disable Add file to current project when saving the files.
  1. Create new blinking_led_slow.sv, blinking_led_empty.sv, and top_counter_fast.sv SystemVerilog files in your working directory. Confirm that blinking_led.sv is already present in the working directory.
  2. Enter the following contents for the SystemVerilog files:
    Table 2.  Reference Design Personas SystemVerilog
    File Name Description Code
    blinking_led_slow.sv LEDs blink slower 
    `timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_slow (
     // clock
     input wire clock,
     input wire reset,
     input wire [31:0] counter,
     // Control signals for the LEDs
     output wire led_two_on,
     output wire led_three_on
);

     localparam COUNTER_TAP = 27;

     reg led_two_on_r;
     reg led_three_on_r;
 
     assign led_two_on = led_two_on_r;
     assign led_three_on = led_three_on_r;

     always_ff @(posedge clock) begin
          led_two_on_r <= counter[COUNTER_TAP];
          led_three_on_r <= counter[COUNTER_TAP];
     end

endmodule
    blinking_led_empty.sv LEDs stay ON 
    `timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_empty(
     // clock
     input wire clock,
     input wire reset,
     input wire [31:0] counter,
     // Control signals for the LEDs
     output wire led_two_on,
     output wire led_three_on
);

     // LED is active low 
     assign led_two_on = 1'b0;
     
     assign led_three_on = 1'b0;

endmodule
    top_counter_fast.sv Second SUPR persona 
    `timescale 1 ps / 1 ps
`default_nettype none 

module top_counter_fast (
     // Control signals for the LEDs
     output wire led_one_on,
     output wire [31:0] count,
     // clock
     input wire clock
);

     localparam COUNTER_TAP = 23;
     reg [31:0] count_d;

     assign count = count_d;
     assign led_one_on = count_d[COUNTER_TAP];

     always_ff @(posedge clock) begin
         count_d <= count_d + 2;
     end
endmodule
  3. Click File > Save As and save the .sv files in the current project directory.
Level Two Title