AN 987: Static Update Partial Reconfiguration Tutorial: for Intel Agilex® 7 FPGA Development Board

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ID 749443
Date 1/16/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Define Personas 1.5.5. Step 5: Create Revisions 1.5.6. Step 6: Compile the Base Revision 1.5.7. Step 7: Set Up PR Implementation Revisions 1.5.8. Step 8: Change the SUPR Logic 1.5.9. Step 9: Program the Board 1.5.10. Modifying the SUPR Partition
1.5.5. Step 5: Create Revisions x
1.5.5.1. Setting the Base Revision 1.5.5.2. Creating Implementation Revisions
1.5.9. Step 9: Program the Board x
1.5.9.1. Troubleshooting PR Programming Errors
Answers to Top FAQs
1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board

1.4. Download Reference Design Files

The partial reconfiguration tutorial is available in the following location:

https://github.com/intel/fpga-partial-reconfig

To download the tutorial:

  1. Click Clone or download.
  2. Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
  3. Navigate to the appropriate subfolder for your F-Series or M-Series device:
    • tutorials/agilex7f_pcie_devkit_blinking_led_supr
    • tutorials/agilex7m_pcie_devkit_blinking_led_supr

The flat subfolder consists of the following reference design files:

Table 1.  Reference Design Files
File Name Description
top.sv

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.

top_counter.sv Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc

Defines the timing constraints for the project.

blinking_led.sv In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].
blinking_led.qpf

Intel® Quartus® Prime project file containing the list of all the revisions in the project.

blinking_led.qsf

Intel® Quartus® Prime settings file containing the assignments and settings for the project.

Note: The supr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.
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