Figure 4. Example Design Tab in the Triple-Speed Ethernet Intel® FPGA IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
2. Select Agilex™ 7 device family and select a device that has LVDS.
3. Click Finish to close the wizard.
4. In the IP Catalog, locate and select Interface Protocol > Ethernet > 1G Multi-rate Ethernet > Triple-Speed Ethernet Intel FPGA IP. The New IP Variation window appears.
5. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
6. Click OK. The parameter editors appears.
7. To generate a design example, select a Multi channel Triple Speed Ethernet MAC PCS Example Design (Agilex) preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The parameter editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab.
8. To generate a design example, select a 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2xTBI PCS and PMA(GTS) preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The parameter editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab.
9. For Example Design Files, select the Simulation option to generate the testbench, or the Synthesis option to generate the hardware design example.
   Note: You must select at least one of the options to generate the design example.
10. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL.
    Note: If you select VHDL, you must simulate the testbench with a mixed language simulator. The device under test is a VHDL model, but the main testbench file is a System Verilog file.
11. Under Target Development Kit, select the Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile) or select None.
    Note:

    1. If you select a specific development kit as the Target Development Kit, the design example is generated based on the specific device and overwrites the device you selected in your project file.
    2. If you select None as the Target Development Kit, ensure that the selected device is your targeted device and adjust the pins assignment in the .qsf file. By default, the .qsf file is generated based on the device used in the development kit.
12. Click the Example Design: “example_design” button. The Select Example Design Directory window appears.
13. If you want to modify the design example directory path or name from the defaults displayed (eth_tse_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
    Note: You must perform the parameter settings based on the steps above to generate the design example.
14. Click OK.