Triple-Speed Ethernet Agilex® 7 FPGA IP Design Example User Guide

Download PDF
ID 741330
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide

2.4.1. Testbench

Figure 8. Block Diagram of the Design Example Multiport 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS with LVDS I/O Simulation Testbench

A successful testbench sends ten packets and receives the same number of packets. The following sample output illustrates the excerpt of the output:

Figure 9. Simulation Test Result of VCS Simulator 
Statistics MAC Tx Path

      — Frames sent in TX path total:      10
      — Tx_good_sent:        10
      — Tx_vlan_sent:         0
      — Tx_stack_vlan_sent:      0
      — Payload_err_sent:        0

Statistics MAC Rx Path — Loopback Test

      — Rx_good_rcvd:        10
      — Rx_vlan_rcvd:         0
      — Rx_stack_vlan_rcvd:      0
      — Rx_fifo_overflow_rcvd:   0
      — Rx_payload_err_rcvd:     0
      — Rx_crc_err_rcvd:         0

-- The total number of good packets received by the traffic monitor:      10

-- The total number of packets received with CRC error:    0

-- Loopback Simulation Ended with no Error

- -------------------------------------------------------------------------- -

End of Simulation — Break

$finish called from file "basic_avl_tb_top_mac_pcs.sv", line 5380.
$finish at simulation time        327000000000
            V C S  S i m u l a t i o n  R e p o r t
Time: 327000000000 fs
CPU Time:    259.890 seconds;        Data structure size:    9.3Mb
Level Two Title