Triple-Speed Ethernet Agilex® 7 FPGA IP Design Example User Guide

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ID 741330
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide

2.3.1. Design Components

Table 5.  Design Components
Component Description
Triple-Speed Ethernet Intel® FPGA IP

The Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) is instantiated with the following configuration:

  • Core Configurations:
    • Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS
    • Use internal FIFO: Not selected
    • Number of ports: 4
    • Transceiver type: LVDS I/O
  • MAC Options:
    • Enable MAC 10/100 half duplex support: Selected
    • Enable local loopback on MII/GMII: Selected
    • Enable supplemental MAC unicast addresses: Not selected
    • Include statistics counters: Selected
    • Enable 64-bit statistics byte counters: Not selected
    • Include multicast hashtable: Not selected
    • Align packet headers to 32-bit boundary: Not selected
    • Enable full-duplex flow control: Selected
    • Enable VLAN detection: Not selected
    • Enable magic packet detection: Selected
    • Include MDIO module (MDC/MDIO): Selected
    • Host clock divisor: 50
  • Timestamp Options:
    • Enable timestamping: Not selected
  • PCS/Transceiver Options:
    • Enable SGMII bridge: Selected
Client Logic Generates and monitors packets sent or received through the IP.
Ethernet Traffic Controller Controlled via Avalon® memory-mapped interface.
JTAG to Avalon® memory-mapped interface Address Decoder Convert JTAG Signals for Avalon® memory-mapped interface.
Level Two Title