Triple-Speed Ethernet Agilex® 7 FPGA IP Design Example User Guide

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ID 741330
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure 2.5.2. Design Constraints
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide

2.1. Features

  • Generates the design example for Triple-Speed Ethernet Multiport Ethernet MAC without Internal FIFO and PCS with LVDS I/O using multi-channel shared FIFO.
  • Generates traffic at the transmit path and validates received data through the transceiver LVDS I/O external loopback.
  • TX and RX serial loopback mode.
  • Supports only external loopback.
  • Supports only two ports.
  • Supports packet statistics report on both MAC transmitter and MAC receiver.
  • Supports System Console user interface. You can make use of the TCL-based user interface to dynamically configure and monitor any registers in this design example.
  • Basic packet checking capabilities of traffic monitor.
Level Two Title