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2.2.1.1. Common Port Mux Interface
2.2.1.2. Common Port Demux Interface
2.2.1.3. Controlled Port Mux Interface
2.2.1.4. Controlled Port Demux Interface
2.2.1.5. Uncontrolled Port RX Interface
2.2.1.6. Uncontrolled Port TX Interface
2.2.1.7. Crypto RX Interface
2.2.1.8. Crypto TX Interface
2.2.1.9. Management Interface
2.2.1.10. Decrypt Port Mux Management Interface
2.2.1.11. Decrypt Port Demux Management Interface
2.2.1.12. Encrypt Port Mux Management Interface
2.2.1.13. Encrypt Port Demux Management Interface
2.2.1.14. Crypto IP Management Bus
2.2.2.1. Common Port Mux Interface Waveform
2.2.2.2. Common Port Demux Interface Waveform
2.2.2.3. Controlled Port Mux Interface Waveform
2.2.2.4. Controlled Port Demux Interface Waveform
2.2.2.5. Uncontrolled Port RX Interface Waveform
2.2.2.6. Uncontrolled Port TX Interface Waveform
2.2.2.7. Crypto RX Waveform
2.2.2.8. Crypto TX Waveform
2.2.2.9. MACsec Management Interface (Read)
2.2.2.10. MACsec Management Interface (Write)
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Ixiasoft
3.1. MACsec Intel FPGA IP Parameter Settings
Parameter | Supported Values | Default Settings | Parameter Description |
---|---|---|---|
Topology Tab | |||
Control Port |
|
ENCRYPT_DECRYPT | Controlled ports for encryption and decryption lanes. |
User Mux Enable | Enable, Disable | ENABLE | Enables the Arbiter on the user interface. |
Uncontrolled Port Enable | Enable, Disable | DISABLE | Indicates whether the uncontrolled ports for both transmit and receive lanes are enabled to receive user traffic. When disabled, the uncontrolled ports are hidden from the user. |
Number of TX+RX Ports | 2-64 | 4 | Maximum number of controlled ports supported in MACsec for all ports and streams. |
Number of TX Ports | 0-64 | 2 | Number of TX ports used in MACsec IP. |
Maximum Crypto Channels | 1024 | 1024 | Maximum number of Crypto channels used in MACsec for all ports and streams. |
Interface Property Tab | |||
Select Port | 0-64 | 0 | Selects the port for which parameters are to be configured. |
User Data Width | 256 and 512 | 512 | AXI-ST User User Interface data bus width. |
Port Data Width |
|
64 | Arbiter data bus width |
Number of Segments | 1-8 | 1 | Cannot be changed. Defines the number of segments supported for a particular data transfer clock. The data bus is segmented evenly based on the number of segments. |
Arbiter Ready Latency | 0-16 | 0 | Defines the association between assertion of the READY signal and the corresponding VALID on the Arbiter interface. |
Buffer Store Forward Enable | 0,1 | 0 | Buffer operates in store and forward mode when enabled. In store and forward mode, the buffer stores the entire packet from the SOP until TLAST/EOP before indicating transfer readiness at the buffer outlet. |
User Metadata Width | 16 | 16 | User metadata signal bit width |
Metadata Enable | Enable, Disable | Disable | Indicates there is user metadata which is tag along with incoming/outgoing packet into MACsec IP. It is required to support PTP use case. |
Port Mux/Demux Short Length Packet Handling | 0,1 | 0 | Enabling this parameter enables the Adapter module that takes care of the short length packet. |
Port Mux Buffer Full Error Checking and Handling | 0,1 | 0 | Enabling this parameter enables the error check to detect the buffer full check of the port Mux buffer. |
Port Demux Buffer Full Error Checking and Handling | 0,1 | 0 | Enabling this parameter enables the error check to detect the buffer full check of the port Demux buffer. |
801_1AE-2018 Options Tab | |||
Editing Port | 0 | 0 | Arbiter Port Parameters |
Port Confidential Offset | 0,30,50 | 0 | Indicates the number of octets after SecTAG that is integrity protected only while remaining octets are confidential and integrity protected. |
Port VLAN Clear | Enable, Disable | Enable | Defines whether VLLAN Clear is supported for Port X. |
Validate Frames | Strict, Check, Disable | Strict | Indicates the transmitted/received frames check level. |
Protect Frames | True, False | True | Frames Protection Enable |
Replay Protect | True, False | True | Anti-Replay Protection Check Enable |
XPN Mode | 0,1 | 1 | Indicates whether the 64b Extended Packet Number is supported. |
Cipher Suite | GCM-AES | GCM-AES | MACsec supports AES-GCM cipher suite. |
Optional Settings Tab | |||
SADB TX STATS DEBUG EN | 0,1 | 1 | Enables stats counter for SADB TX. |
SADB RX STATS DEBUG EN | 0,1 | 1 | Enables stats counter for SADB RX. |
PORT MUX CSR MUX EN | 0,1 | 1 | Enables MUX CSR. Valid when CSR_MUX_EN_BUF is set to "1". |
PORT MUX CSR MUX BUF EN | 0,1 | 1 | Enables MUX Buffer CSR. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX ACT CTRL REG EN | 0,1 | 0 | Enables Default Action Control register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX HI WM_REG EN | 0,1 | 0 | Enables High Watermark register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX LO WM_REG EN | 0,1 | 0 | Enables Low Watermark register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX BUF CTRL_REG EN | 0,1 | 1 | Enables Store and Forward register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX BUF STS_REG EN | 0,1 | 0 | Enables Buffer status register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX TRUNC STS_REG EN | 0,1 | 0 | Enables Truncated packet status register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT MUX DISC STS_REG EN | 0,1 | 0 | Enables Discarded packet status register. Valid when CSR_MUX_BUF_EN is set to "1". |
PORT DEMUX CSR DEMUX EN | 0,1 | 0 | Enables DEMUX CSR. Valid when CSR_DEMUX_EN is set to "1". |
PORT DEMUX CSR DEMUX BUF EN | 0,1 | 0 | Enables DEMUX Buffer CSR. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX ACT CTRL REG EN | 0,1 | 0 | Enables Default Action Control register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX HI WM REG EN | 0,1 | 0 | Enables High Watermark register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX LO WM REG EN | 0,1 | 0 | Enables Low Watermark register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX BUF CTRL REG EN | 0,1 | 0 | Enables Store and Forward register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX BUF STS REG EN | 0,1 | 0 | Enables Buffer status register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX TRUNC STS REG EN | 0,1 | 0 | Enables Truncated packet status register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
PORT DEMUX DISC STS REG EN | 0,1 | 0 | Enables Discarded packet status register. Valid when CSR_DEMUX_BUF_EN is set to "1". |
USER PORT MULTI | Enable, Disable | Disable | Indicates the AXI-ST Controlled/Common port is operating in Single Packet Mode or Multi Packet Mode. |
Engineering Settings Tab | |||
Hidden Parameters Enable | Unchecked, Checked | Unchecked | Shows the hidden parameters. |
CRYPTO_QHIP_EN | 0,1 | 1 | Enables AES Crypto-IP |
REPLAY_PROTECT_MULTI_CYCLE | 0,1 | 0 | Enables Multi-Cycle Implementation of the Anti-Replay Protection Check Enable feature. |
Ethernet Channel Width |
|
64 | Defines supported Ethernet Channel Width. |
FRAMER_STALL_WATERMARK | 192 | 192 | FIFO watermark on Framer |
AGGR_FIFO_WATERMARK | 10 | 10 | FIFO watermark on Aggregator |
DEAGGR_FIFO_WATERMARK | 5 | 5 | FIFO watermark on Disaggregator |
AES_PORT_READYLATENCY_VLD | 1-14 | 3 | Defines the association between assertion of READY signal and the corresponding VALID on AES interface |
AES_PORT_READYLATENCY_RDY | 1-15 | 2 | Defines the association between assertion of READY signal and the corresponding VALID on AES interface |
MACsec Debug Testbus Enable | Enable, Disable | Disable | sTAP Enhancement |
TX Controlled Uncontrolled Priority | CTRL | CTRL | Priority of Arbitration MUX: Controlled/Uncontrolled Ports |
MACsec Debug CSR Enable | Enable, Disable | Disable | Enabling the Debuggability feature on MACsec |
Example Designs Tab | |||
Example Design Files | |||
Simulation | Checked, Unchecked | Checked | When the Simulation box is checked, all necessary file sets required for simulation are generated. When this box is NOT checked, file sets required for simulation are NOT generated. Instead a gsys example design system is generated. |
Synthesis | Checked, Unchecked | Checked | When the Synthesis box is checked, all necessary file sets required for synthesis are generated. When this box is NOT checked, file sets required for synthesis are NOT generated. Instead a gsys example design system is generated. |
Generated HDL Format | |||
General file format | Verilog | Verilog | HDL format |
Target Development Kit | |||
Current development kit | None | None | This option provides support for various development kits listed. The details of Intel FPGA development kits can be found on Intel the Intel FPGA website: http://www.altera.com/product/boards_and kits/all-development-kits.html. If this menu is greyed out, it because no board is supported for the options selected (for example, synthesis deselected) If an Intel FPGA development board is selected, the Target Device used for generation is the one that matches the device on the development kit. |