MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/21/2022
Public

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Document Table of Contents

2.2.1.14. Crypto IP Management Bus

Note: For the applicable register map, refer to Symmetric Cryptographic Intel FPGA Hard IP User Guide.
Table 20.  Crypto IP Management Bus
Signal Name Width Direction Description
crypto_clk 1 Input Clock port for the Symmetric Cryptographic IP core clock. This clock supports 600Mhz frequency.
crypto_app_ip_lite_awaddr 25 Input Write Address
crypto_app_ip_lite_awprot 3 Input Privilege and security level of the transaction
crypto_app_ip_lite_awvalid 1 Input Write address valid
crypto_ip_app_lite_awready 1 Output Indicates slave is ready to accept a write transaction
crypto_app_ip_lite_wdata 64 Input Write data
crypto_app_ip_lite_wstrb 8 Input Indicates the byte lanes that hold valid data
crypto_app_ip_lite_wvalid 1 Input Write data valid
crypto_ip_app_lite_wready 1 Output Indicates that the slave can accept the write data
crypto_ip_app_lite_bresp 2 Output Indicates the status of the write transaction
crypto_ip_app_lite_bvalid 1 Output Write response valid
crypto_app_ip_lite_bready 1 Input Indicates that the Master can accept a write response
crypto_app_ip_lite_araddr 25 Input Read Address
crypto_app_ip_lite_arprot 3 Input Read address channel privilege and security attribute
crypto_app_ip_lite_arvalid 1 Input Read address channel valid
crypto_ip_app_lite_arready 1 Output Indicates that the slave can accept a read transaction
crypto_ip_app_lite_rdata 64 Output Read Data
crypto_ip_app_lite_rvalid 1 Output Read data valid
crypto_app_ip_lite_rready 1 Input Indicates that the Master can accept the read data and response
crypto_ip_app_lite_rresp 2 Output Indicates the status of the read transaction