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Ixiasoft
Visible to Intel only — GUID: hrr1654714715225
Ixiasoft
3.2. Simulink* Model
Top-level Overview
The load current is simulated as a square waveform with positive and negative values, generating current and voltage waveforms inside the design. When the load current switches, you can examine the transient current and voltage signals using the rectifier.stp file in Signal Tap logic analyzer within the Intel® Quartus® Prime software on a computer.
The following image shows the expanded three-phase boost bidirectional AC/DC converter block:
The bidirectional AC/DC converter block has the portion of the simulation for which VHDL code is generated. The outputs are defined in the top-level model file using the blocks' in-port or out-port port interfaces for the VHDL code. The MATLAB Simulink in-port and out-port signals define the VHDL signal names, and the VHDL data formats are the signal formats you typically set with the convert block.