AN 973: Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging

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ID 733436
Date 6/23/2022
Public
Document Table of Contents
Document Table of Contents x
1. Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging Design Example Overview 2. Downloading and Installing the Design Example 3. Model Description 4. FPGA Resource Use Comparison 5. Locating Top-level VHDL Wrapper 6. Generating HDL Code with MATLAB and HDL Coder 7. Simulink Simulation Results 8. Document Revision History for AN 973: Three-phase Boost Bidirectional AC/DC Converter for EV Charging
2. Downloading and Installing the Design Example x
2.1. Software Requirements 2.2. Hardware Requirements 2.3. Downloading and Installing the Design
3. Model Description x
3.1. Simscape* Model 3.2. Simulink* Model 3.3. HDL Inputs, Outputs, and Parameters
3.2. Simulink* Model x
3.2.1. Controller Block 3.2.2. Power Electronics Block Model 3.2.3. Source Voltage Generator Block
3.2.1. Controller Block x
3.2.1.1. Pulse Width Modulation (PWM) Controller 3.2.1.2. Phase-locked Loop (PLL) 3.2.1.3. Sampling Circuit 3.2.1.4. Clarke and Park Transforms
3.2.2. Power Electronics Block Model x
3.2.2.1. Six-switch Power Converter 3.2.2.2. Inductors 3.2.2.3. Output Capacitor
6. Generating HDL Code with MATLAB and HDL Coder x
6.1. Generating HDL and QPF Using MATLAB Scripts 6.2. Generating HDL and QPF Using MATLAB GUI Tools
1. Three-phase Boost Bidirectional AC/DC Converter for Electric Vehicle (EV) Charging Design Example Overview
2. Downloading and Installing the Design Example
3. Model Description
4. FPGA Resource Use Comparison
5. Locating Top-level VHDL Wrapper
6. Generating HDL Code with MATLAB and HDL Coder
7. Simulink Simulation Results
8. Document Revision History for AN 973: Three-phase Boost Bidirectional AC/DC Converter for EV Charging

3.3. HDL Inputs, Outputs, and Parameters

The following tables list the inputs, outputs, and PI controller block parameters on the HDL coder block:

Table 2.  Inputs for HDL Coder Block
Input Signal Name Type Description
clk Clock Input clock for the HDL coder block. Generated by PLL 20 MHz.
reset Reset Active low reset
clk_enable Enable Active high reset
Table 3.  Outputs for HDL Coder Block
Output Signal Name Data Type Description

V_R_L_diff

V_Y_L_diff

V_B_L_diff

Fix32_En16 The voltage across inductors for debugging when compared to the input voltage.
V_R, V_Y, V_B Fix32_En16 Three-phase input voltage from the voltage generator block.
I_R, I_Y, I_B Fix32_En16 Measured current in each inductor model block.
I_LOW, I_HIGH Fix32_En16 Sum of the low and high-side switch currents, respectively
VDC_P, VDC_N Fix32_En16 Voltage relative to ground of the DC output +/- ports.
I_C Fix32_En16 Current measured in the output capacitor.
I_LOAD Fix32_En16 Current measured in the output load.
V_RYB_SUM Fix32_En16 Sum of the input AC voltages.
PWM_SUM Fix32_En16 Sum of the three PWM-generated signals by the controllers.
PWM_R, PWM_Y, PWM_B Fix32_En16 Controller-generated PWM signals for power transistor switching.
Table 4.  PI Controller Block Parameters
PI Controller Block Parameters Value
Voltage Loop Pgain 0.075
Voltage Loop Igain 22 * Ts
Dcurrent Loop Pgain 11
Dcurrent Loop Igain 500 * Ts
Qcurrent Loop Pgain 12.5
Qcurrent Loop Pgain 500 * Ts
Level Two Title