F-Tile JESD204B Intel® FPGA IP Design Example User Guide

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ID 729497
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

3.2.2. Parallel I/O Core

The Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon® master (JTAG to Avalon® master bridge). There are two sets of 32-bit PIO registers:

  • Status registers—input from the HDL components to the Avalon® master
  • Control registers—output from the Avalon® master to the HDL components

The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.

Table 13.  Signal Connectivity for Status Registers
Bit Signal
0 Core PLL locked
1 TX reset handshake acknowledge status (jesd204_tx_rst_ack_n)
2 RX reset handshake acknowledge status (jesd204_rx_rst_ack_n)
3 Test pattern checker data error (for duplex and simplex RX data path only)
4 TX link error (for duplex and simplex TX data path only)
5 RX link error (for duplex and simplex RX data path only)
31:6 Reserved
Table 14.  Signal Connectivity for Control Registers
Bit Signal
29:0 Reserved
30 Global reset
31 SYSREF
Level Two Title