F-Tile JESD204B Intel® FPGA IP Design Example User Guide

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ID 729497
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

2.1. Design Example Block Diagram

Figure 2.  F-Tile JESD204B Design Example High-level Block Diagram

The design example consists of the following modules:

  • Platform Designer system
    • JESD204B subsystem
      • F-Tile JESD204B Intel® FPGA IP
      • F-Tile Reference and System PLL Clocks IP
      • Reset sequencers
      • Avalon® memory-mapped bridge
    • JTAG to Avalon master bridge—for System Console control design example only
    • Parallel I/O (PIO) controller
    • Core PLL
    • Serial Port Interface (SPI)—master module
  • Test pattern generator (for duplex and simplex TX data path only)
  • Test pattern checker (for duplex and simplex RX data path only)
  • Assembler—TX transport layer (for duplex and simplex TX data path only)
  • Deassembler—RX transport layer (for duplex and simplex RX data path only)
Level Two Title