AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC

Download PDF
ID 723698
Date 5/11/2015
Public
Document Table of Contents
Document Table of Contents x
1. Remote Hardware Debugging over TCP/IP for Altera SoC
1. Remote Hardware Debugging over TCP/IP for Altera SoC x
1.1. TCP/IP Communication Channel 1.2. Use-Case Scenarios 1.3. Software Requirements 1.4. Hardware Requirements 1.5. System Components 1.6. How to Remote Debug with the SignalTap II Logic Analyzer 1.7. Appendix 1.8. Document Revision History
1.5. System Components x
1.5.1. The Processor 1.5.2. SLD Hub Controller 1.5.3. SLD Hub
1.5.3. SLD Hub x
1.5.3.1. Supported System Debugging Tools
1.6. How to Remote Debug with the SignalTap II Logic Analyzer x
1.6.1. Example Implementation of Remote Debugging on an Altera SoC (5CSXSoC)
1. Remote Hardware Debugging over TCP/IP for Altera SoC

1.1. TCP/IP Communication Channel

Historically, the Altera System-Level Debugging (SLD) communication solution was based on the Altera JTAG Interface (AJI) which interfaced with the JTAG TAP controller (hard atom in Altera devices which implements the JTAG protocol). The SLD tools (SignalTap II Logic Analyzer, In-System Sources and Probes (ISSP), In-System Memory Content Editor) and the Nios II on-chip instrumentation (OCI) use the JTAG channel for communication between software and hardware. To support communication via TCP/IP, the SLD Hub Controller replaces the JTAG TAP controller.
Figure 1. TCP/IP Communication Channel Block Diagram


Level Two Title