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1.6. How to Remote Debug with the SignalTap II Logic Analyzer
To implement remote debugging for the SignalTap II Logic Analyzer over TCP/IP, follow these steps:
- Verify your design can run a TCP server with memory-mapped access to the device.
For Altera SoC, the Linux kernel handles the TCP/IP connection.
- Instantiate the SLD Hub Controller System component from the IP Catalog.
Figure 4. SLD Hub Controller System
- Generate the Qsys system.
- Tap some nodes using SignalTap II Logic Analyzer.
- Compile the design.
- Using the existing remote configuration setup, update the remote board with firmware which contains the SLD Hub Controller System instantiated in the FPGA over the TCP server (enabled to listen for incoming debug connections).
- Start System Console in JTAG server mode using the Tcl script in the Reference Design or using a custom script.
System-console-jtag_server-rc_script=mmlink_setup.tcl<path to .sof><IP><port number>
- After connecting, start the SignalTap II Logic Analyzer. You should see a System Console cable as an option under Hardware.
Figure 5. Successfully Connected in SignalTap II Logic Analyzer