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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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6.1.1.1. Obtaining RSKM Report
For LVDS receivers, the Intel® Quartus® Prime software generates the RSKM report (report_rskm) that provides the SW, TUI or LVDS period, and RSKM values for the non-DPA mode.
Before you begin, compile your project and ensure that the compilation is successful.
- From the Intel® Quartus® Prime menu, select Tools > Timing Analyzer.
The Timing Analyzer window appears.
- In the Task pane of the Timing Analyzer window, double-click Update Timing Netlist.
- From the Timing Analyzer menu, select Reports > IP Specific > Report RSKM.