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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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3.3. Differential I/O Bit Position
Successful high frequencies data transmission requires data synchronization.
Figure 6. Bit-Order and Word Boundary for One Differential Channel
This figure shows the data bit orientation for a channel operation, based on the following conditions:
- The serialization factor is equal to the clock multiplication factor.
- The phase alignment uses edge alignment.
- The operation is implemented in the hard SERDES.
Transmitter Channel Data Number | Internal 8-Bit Parallel Data | |
---|---|---|
MSB Position | LSB Position | |
1 | 7 | 0 |
2 | 15 | 8 |
3 | 23 | 16 |
4 | 31 | 24 |
5 | 39 | 32 |
6 | 47 | 40 |
7 | 55 | 48 |
8 | 63 | 56 |
9 | 71 | 64 |
10 | 79 | 72 |
11 | 87 | 80 |
12 | 95 | 88 |