ID
721819
Date
11/30/2022
Public
Visible to Intel only — GUID: cjn1629100033664
Ixiasoft
1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
Visible to Intel only — GUID: cjn1629100033664
Ixiasoft
1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
Updated for: |
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Intel® Quartus® Prime Design Suite 22.1 |
The Intel® Agilex™ F-series and I-series I/O system includes three types of I/O interfaces: general purpose I/Os (GPIO), Secure Device Manager (SDM) I/O, and Hard Processor System (HPS) I/O. Each I/O interface caters to different interfacing requirements.
Intel® Agilex™ F-series and I-series devices support LVDS serializer/deserializer (SERDES) through the True Differential Signaling I/Os in the GPIO banks. The true differential I/Os are capable of supporting LVDS interfaces, including subsets such as:
- RSDS
- Mini-LVDS
- Any I/O standards using equivalent electrical specifications
Intel® Agilex™ F-series and I-series devices support SERDES on all True Differential Signaling GPIO banks with the following features:
- SERDES interfaces up to 1.6 Gbps.
- Differential 100-ohm OCT RD.
- Differential I/O reference clock for the I/O PLL that drives the SERDES.
- Dedicated transmitter and dedicated receiver differential pin pairs in each I/O bank with multiple usage modes options.
- In each I/O bank, there are 24 receiver channels with SERDES and DPA, and 24 transmitter channels with SERDES. The total number of SERDES channels varies across Intel® Agilex™ devices, depending on the total number of pins available in the package.