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1. Intel® Agilex™ F-Series and I-Series LVDS SERDES Overview
2. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Architecture
3. Intel® Agilex™ LVDS SERDES Transmitter
4. Intel® Agilex™ LVDS SERDES Receiver
5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
6. Intel® Agilex™ LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Design Guidelines
9. Intel® Agilex™ F-Series and I-Series High-Speed SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
11. Document Revision History for the Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide
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5. Intel® Agilex™ High-Speed LVDS I/O Implementation Guide
You can implement your high-speed LVDS I/O design using the LVDS SERDES Intel® FPGA IP in the Intel® Quartus® Prime software. The software contains tools for you to create and compile your design, and configure your device.
The Intel® Quartus® Prime software allows you to prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize the LVDS SERDES IP.