6.5. XGMII Signals
Signal Name | Direction | Width | Description | |||||||||||||||
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XGMII Transmit —synchronous to xgmii_tx_coreclkin | ||||||||||||||||||
xgmii_tx_control | Input | 4 | TX control from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. The xgmii_tx_control bit corresponds to the xgmii_tx_data bits. For example, xgmii_tx_control[0] corresponds to xgmii_tx_data[7:0], xgmii_tx_control[1] corresponds to xgmii_tx_data[15:8], and so on. |
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xgmii_tx_data | Input | 32 | TX data from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. The MAC sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on. |
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xgmii_tx_valid | Output | 1 | Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
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xgmii_tx_latency | Output | 24 | TX XGMII datapath latency for IEEE 1588. Measured from XGMII user interface to PCS-PMA interface.
This signal is available only when the IEEE 1588 feature is enabled. |
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XGMII Receive —synchronous to xgmii_rx_coreclkin | ||||||||||||||||||
xgmii_rx_control | Output | 4 | RX control to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. The xgmii_rx_control bit corresponds to the xgmii_rx_data bits. For example, xgmii_rx_control[0] corresponds to xgmii_rx_data[7:0], xgmii_rx_control[1] corresponds to xgmii_rx_data[15:8], and so on. |
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xgmii_rx_data | Output | 32 | RX data to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. The PHY sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on. |
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xgmii_rx_valid | Output | 1 | Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
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xgmii_rx_latency | Output | 24 | RX XGMII datapath latency for IEEE 1588. Measured from XGMII user interface to PCS-PMA interface.
This signal is available only when the IEEE 1588 feature is enabled. |