6.1. Clock Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
csr_clk | Input | 1 | Clock for the Avalon® memory-mapped interface control and status interface. Intel recommends 100 to 156.25 MHz for this clock. |
xgmii_tx_coreclkin | Input | 1 | TX clock for the XGMII logic before phase compensation FIFO. Provides a 312.5 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. |
xgmii_rx_coreclkin | Input | 1 | RX clock for the XGMII logic after rate matcher. Provides a 312.5 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. |
tx_pma_clk | Input | 1 | TX clock of soft PCS (interface with F-Tile Ethernet Hard IP). Provides a 322.265625 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. Tie this signal to o_clk_pll. |
rx_pma_clk | Input | 1 | RX clock of soft PCS (interface with F-Tile Ethernet Hard IP). Provides a 322.265625 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. Tie this signal to o_clk_pll. |
o_clk_pll | Output | 1 | 322.265625 MHz clock derived from the F-Tile System PLL associated with this Ethernet Port. The frequency is the system PLL frequency divided by 2 Source i_tx_clk_clk and i_rx_clk_clk from o_clk_pll of this or another IP on the same system clock, or a parts per million (ppm)-matched clock of the same frequency. Do not use o_clk_pll until o_sys_pll_locked is asserted. Refer to Clocking for the details on clock connectivity. |
i_tx_clk_clk | Input | 1 | 322.265625 MHz TX datapath clock. This signal drives the active TX Interface for the port. Source this signal from o_clk_pll. |
i_rx_clk_clk | Input | 1 | 322.265625 MHz RX datapath clock. This signal drives the active RX Interface for the port. Source this signal from o_clk_pll. |
i_reconfig_clk | Input | 1 | Reconfiguration clock for Avalon® memory-mapped interfaces (The interface uses this clock to access Ethernet reconfiguration and transceiver reconfiguration of the F-Tile Ethernet Hard IP). Intel recommends 100 to 156.25 MHz for this clock. |
i_clk_ref | Input | 1 | 156.25/312.5/322.2656 MHz transceiver reference clock (from F-Tile Reference and System PLL Clocks IP). This port connects to a virtual “Link” net that carries no signal.
Note: The i_clk_ref is a virtual signal. In simulation, the signal displays as 0.
|
i_clk_sys | Input | 1 | 644.53125 MHz Ethernet system clock (from F-Tile Reference and System PLL Clocks IP).
Note: The i_clk_sys is a virtual signal. In simulation, the signal displays as 0.
|
i_clk_pll | Input | 1 | This clock signal is unused. Tie this signal to ground. |
latency_sclk | Input | 1 | Sampling clock to measure the datapath latency. The clock period is 6.5ns. It is available only when IEEE 1588 feature is enabled. |
rx_pma_clkout | Output | 1 | 156.25 MHz clock derived from the RX (recovered) serdes rate per stream divided by 66. |