F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

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ID 720989
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers 8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive 9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IPs 3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IPs x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-Tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Operation Speed Switching 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII 4.6. IEEE 1588 Precision Time Protocol
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

6.7. Reconfiguration Signals

The Ethernet Reconfiguration Interface (reconfig_eth) provides access to the F-Tile Ethernet Hard IP Avalon memory-mapped interface space. This interface is word-addressed. The address always aligns to 32-bit words. the Ethernet reconfiguration register access described in this user guide is byte-based access. You need to convert each word address to a byte address by shifting right by two (dividing by 4). To access individual bytes, use the byte enable signal.

The Transceiver Reconfiguration interface (reconfig_xcvr) provides access to the F-tile transceiver Avalon memory-mapped interface space.

The signals in both Reconfiguration Interfaces are clocked by i_reconfig_clk clock and reset by the i_reconfig_reset signal.

Refer to the F-Tile Ethernet Hard IP User Guide and F-Tile Architecture and PMA and FEC Direct PHY IP User Guide for more information.

Table 21.  Reconfiguration Signals
Signal Name Direction Width Description
Ethernet Reconfiguration Interfaces—synchronous to i_reconfig_clk
i_reconfig_eth_addr Input 14 Address for the Ethernet CSRs (word-addressed).
i_reconfig_eth_read Input 1 Read command for the Ethernet CSRs.
i_reconfig_eth_write Input 1 Write command for the Ethernet CSRs.
i_reconfig_eth_byteenable Input 4 Byte enable for read/write to the Ethernet CSRs.
o_reconfig_eth_readdata Output 32 Read data from reads to the Ethernet CSRs.
o_reconfig_eth_readdata_valid Output 1 Read data from the Ethernet CSRs is valid.
i_reconfig_eth_writedata Input 32 Data for writes to the Ethernet CSRs.
o_reconfig_eth_waitrequest Output 1 Avalon® memory-mapped stalling signal for operations on the Ethernet CSRs.
Transceiver Reconfiguration Interfaces—synchronous to i_reconfig_clk
reconfig_xcvr_slave_0_address Input 18 Address for the transceiver CSRs (word-addressed).
i_reconfig_xcvr0_read Input 1 Read command for the transceiver CSRs.
i_reconfig_xcvr0_write Input 1 Write command for the transceiver CSRs.
i_reconfig_xcvr0_byteenable Input 4 Byte enable for read/write to the transceiver CSRs.
o_reconfig_xcvr0_readdata Output 32 Read data from reads to the transceiver CSRs.
o_reconfig_xcvr0_readdata_valid Output 1 Read data from the transceiver CSRs is valid.
i_reconfig_xcvr0_writedata Input 32 Data for writes to the transceiver CSRs.
o_reconfig_xcvr0_waitrequest Output 1 Avalon® memory-mapped stalling signal for operations on the transceiver CSRs.
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