F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

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ID 720989
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers 8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive 9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IPs 3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IPs x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-Tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Operation Speed Switching 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII 4.6. IEEE 1588 Precision Time Protocol
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

4. Functional Description

The F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements the 10 Mbps to 10 Gbps Ethernet PHY in accordance to the IEEE 802.3 Ethernet standard. The IP handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10Gbe PCS and PMA (PHY).

Figure 7. Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet 10G MAC Intel® FPGA IP Parameter Editor.
The IP core includes the following interfaces:
  • Datapath client-interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) — XGMII, 32 bits
  • Management interface — There are three Avalon memory-mapped slave interfaces for USXGMII management, Ethernet Hard IP, and transceiver reconfigurations.
  • Datapath Ethernet interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) — Single 10.3125 Gbps serial link.
The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following features:
  • USXGMII—10M/100M/1G/2.5G/5G/10G speeds
  • Full duplex data transmission only
  • USXGMII Auto-Negotiation

Section Content
Clocking and Reset Sequence
Timing Constraints
Operation Speed Switching
IEEE 802.3 Clause 37 Auto-Negotiation
USXGMII
IEEE 1588 Precision Time Protocol

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