F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

4.3. Operation Speed Switching

Table 11.  Operating Speed Switching Methodology
PHY Configuration Speed Switch Methodology
10M/100M/1G/2.5G/5G/10G (USXGMII)

Auto-speed switching via USXGMII Auto-Negotiation or manual speed switching via CSR available inside the PHY.

Table 12.  Supported Operating Speed
PHY Configuration Features 10M 100M 1G 2.5G 5G 10G
10M/100M/1G/2.5G/5G/10G (USXGMII) Protocol 10GBASE-R

1000x data replication

10GBASE-R

100x data replication

10GBASE-R

10x data replication

10GBASE-R

4x data replication

10GBASE-R

2x data replication

10GBASE-R

No data replication

Transceiver Data Rate1 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps
MAC Interface 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz
1 With oversampling for lower data rates.