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1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP
3.2. Installing and Licensing Intel® FPGA IPs
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IPs
3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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4.3. Operation Speed Switching
PHY Configuration | Speed Switch Methodology |
---|---|
10M/100M/1G/2.5G/5G/10G (USXGMII) | Auto-speed switching via USXGMII Auto-Negotiation or manual speed switching via CSR available inside the PHY. |
PHY Configuration | Features | 10M | 100M | 1G | 2.5G | 5G | 10G |
---|---|---|---|---|---|---|---|
10M/100M/1G/2.5G/5G/10G (USXGMII) | Protocol | 10GBASE-R 1000x data replication |
10GBASE-R 100x data replication |
10GBASE-R 10x data replication |
10GBASE-R 4x data replication |
10GBASE-R 2x data replication |
10GBASE-R No data replication |
Transceiver Data Rate1 | 10.3125 Gbps | 10.3125 Gbps | 10.3125 Gbps | 10.3125 Gbps | 10.3125 Gbps | 10.3125 Gbps | |
MAC Interface | 32-bit XGMII @ 312.5 MHz | 32-bit XGMII @ 312.5 MHz | 32-bit XGMII @ 312.5 MHz | 32-bit XGMII @ 312.5 MHz | 32-bit XGMII @ 312.5 MHz | 32-bit XGMII @ 312.5 MHz |
1 With oversampling for lower data rates.