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1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP
3.2. Installing and Licensing Intel® FPGA IPs
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IPs
3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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2.2. Features
Feature | Description |
---|---|
Operating speeds | 10M, 100M, 1G, 2.5G, 5G, and 10G. |
MAC-side interface | 32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T). |
Network-side interface | 10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T). |
Avalon® memory-mapped interface | Provides access to the configuration registers of the PHY. |
PCS function | USXGMII PCS for 10M/100M/1G/2.5G/5G/10G (USXGMII). |
Auto-negotiation | USXGMII auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) configuration. |
IEEE 1588v2 |
Note: For the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration, the provided latency is applicable only for 100M, 1G, 2.5G, 5G, and 10G modes.
|
Sync-E | Provides the clock for Sync-E implementation. |