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1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP
3.2. Installing and Licensing Intel® FPGA IPs
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IPs
3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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4.1.1. Clocking
Figure 8. Clocking Diagram
The ref_clk signal is the reference clock to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. Connect the ref_clk signal to the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP. Intel recommends that you use 156.25 Mhz for the ref_clk signal. Refer to Clock Signals for more details about clock signals.