F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

4.1.1. Clocking

Figure 8. Clocking Diagram

The ref_clk signal is the reference clock to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. Connect the ref_clk signal to the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP. Intel recommends that you use 156.25 Mhz for the ref_clk signal. Refer to Clock Signals for more details about clock signals.