F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

3.7.1. Adding the F-Tile Reference and System PLL IP

Figure 6.  1G/2.5G/5G/10G Multirate Ethernet PHY Interface with F-tile Reference and System PLL Clocks IP

You must connect the F-Tile Reference and System PLL Clocks Intel® FPGA IP to the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP to compile the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP successfully.

The F-Tile Reference and System PLL Clock Intel® FPGA IP configures the reference and system clocks of the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP

For more information, refer to Reference and System PLL Clock for your IP Design in the F-Tile Ethernet Intel FPG Hard IP User Guide.