F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.3
IP Version 22.0.0
The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel FPGA IP User Guide provides the features, architecture description, steps to instantiate, and guidelines for Intel Agilex® 7 F-Tile devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the 1G/2.5G/5G/10G Multirate Ethernet PHY protocol.
Table 1.  Related Documents
Reference Description
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Release Notes Lists the changes made for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP in a particular release.
Intel Agilex® 7 Device Data Sheet

Describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel Agilex® 7 devices.

F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Describes the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP.
F-Tile Ethernet Intel® FPGA Hard IP User Guide Describes the F-Tile Ethernet Intel® FPGA Hard IP.

Acronyms and Glossaries

Table 2.  Acronym List
Acronym Expansion
AIB Advanced interface bus
ALM Adaptive logic element
CSR Control and status register
EMIB Intel Embedded Silicon Bridge technology
FPGA Field Programmable Gate Array
LAB Logic array block
LUT Look-up table
MAC Media Access Control
MLAB Memory Logic Array Block
PCS Physical coding sublayer
PFC Priority-based flow control
PHY Physical layer
PLL Phase-locked loop
PMA Physical medium attachment
PTP Precision Time Protocol