F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 2/03/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
1. Introduction x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Hardware States and Configuration Profiles 4.4. Nios® -Based Dynamic Reconfiguration Flow
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm
1. Introduction
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 4.0.0
The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP allows you to dynamically reconfigure a subset of the transceiver channels to operate in different modes, for example data rates, without impacting the adjacent active channels.
Depending on the protocol and hardware implementation, dynamic reconfiguration (DR) may reconfigure media access control (MAC), forward error correction (FEC), and physical coding sublayer (PCS) blocks, and the embedded multi-die interconnect bridges (EMIB). Additional dynamic reconfiguration features include:
  • Setting up the required reference clocks. The system clock must be constant across all profiles in a selected dynamic reconfiguration group.
  • Selecting the appropriate clocks input for each of the MAC, FEC, PCS, and transceiver blocks
  • Setting the multiplexers to select the appropriate control and data path for MAC/PCS/PMA/FEC-direct modes
The FPGA IP products may support the following dynamic reconfiguration flows:
  • Nios® -based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, and intra protocol link characteristic changes, such as CPRI data rate changes. A client application or an Intel® Quartus® Prime Nios® utility triggers the dynamic reconfiguration. When triggered, the Nios® performs the low level configuration register programming for various functional blocks.
  • Host software-based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, or intra protocol link characteristic changes, such as CPRI data rate changes. The host software runs on an Intel® Xeon® or Arm* processor and performs low level configuration register programming for various functional blocks in the FPGA fabric, such as EMIB, and the tile directly. For this use case, you must refer to the appropriate F-tile based collaterals to build your own solution.
  • Individual protocols-based dynamic reconfiguration: This flow includes intra protocol link characteristics changes such as link width, transmitter swing changes, data rate switching, and mode changes such as FEC types. The individual protocols such as HDMI, DisplayPort, or SDI include built-in state machines and controllers to dynamically change transceiver configuration registers when the link characteristics change.

This document describes the NIOS-based dynamic reconfiguration through the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP. The document also specifies the dynamic reconfiguration programming sequences as references for the software-based dynamic reconfiguration. The individual protocol-based dynamic reconfiguration is not part of this document.

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