F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 2/03/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
1. Introduction x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Hardware States and Configuration Profiles 4.4. Nios® -Based Dynamic Reconfiguration Flow
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm
1. Introduction
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP

5. Block Description

The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP allows you to dynamically reconfigure your design using the Nios® core. This section describes the key building blocks for the IP.
Figure 5. Dynamic Reconfiguration IP Block Diagram

The F-tile provides flexibility to construct a solution that works with the protocols of your choice. In addition to transceiver blocks, multiple optional building blocks such as MAC, PCS, FEC are also available. Each of the protocols can interact with the tile through the respective PMA-Direct, FEC-Direct, PCS-Direct or MAC-Direct interfaces exposed via various IPs. Due to EMIB pin mapping constraints, different *-Direct interfaces are muxed into a single one prior to crossing the EMIB channels. Similarly, the single interface is demuxed appropriately on the other side (i.e. main die). Mapping of the respective *-Direct pins to EMIB channel pins are tile-specific and are treated as black-box by the Dynamic Reconfiguration IP.

The dynamic reconfiguration multiplexer (DR Mux) exposes multiple ports to the soft IP and EMIB channels. The DR Mux provides the flexibility to map multiple protocols to the limited transceiver channels (through the EMIB channels). The Nios® core or host software directly control the multiplexer structure. The DR Mux structure performs the intra or inter-protocol dynamic reconfiguration. Signals connected to the DR Mux ports are passed through without a remapping or additional processing.

The Nios® core or host software perform the inter-protocol and intra-protocol switching:

Inter- and Intra-Protocol Switching: The host software communicates the intent to perform reconfiguration. The software writes additional attributes to the appropriate dynamic reconfiguration CSR registers. After the software initiate a reconfiguration request, the Nios® core executes a series of low level register programming and communicate the completion status to the host software through a dynamic reconfiguration CSR field. The Avalon® memory-mapped interface Arbiter (AVMM Arbiter) serves to arbitrate dynamic reconfiguration CSR access cycles between host software and the Nios® core.

Reset Control Block: The IP communicates the reset request through the F-tile Soft Reset Controller (SRC). The SRC performs the tile reset sequence to reset specific paths during the dynamic reconfiguration process.

Dynamic Reconfiguration CSR (DR CSR): The DR CSR contains registers accessible by host software or Nios® core. If Nios® core facilitates the dynamic reconfiguration, the host software must program the relevant CSRs and then trigger a new configuration. Also, Nios® translates the CSR values into the tile CSR programming sequences.

Dynamic Reconfiguration Multiplexer (DR Mux): The DR Mux performs multiplexing between the dynamic reconfiguration IP protocols and the corresponding EMIB channels. Also, the DR Mux ensures the protocol to transceiver channel mapping meets the requirements of the connector form factors and specifications. The mapping between EMIB channels, transceiver channels, and the datapath through the corresponding blocks (MAC, PCS, FEC) plays a big role in the DR Mux construction.

Avalon® Memory-Mapped Interface Arbiter and Tile Avalon® Memory-Mapped Interface : The Nios® core accesses the tile IPs through the global Avalon® memory-mapped interface. Both, the host software and Nios® arbitrates for access to the dynamic reconfiguration CSR and Avalon® memory-mapped interface fabric.

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