F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 2/03/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
1. Introduction x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Hardware States and Configuration Profiles 4.4. Nios® -Based Dynamic Reconfiguration Flow
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm
1. Introduction
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP

6.2. Dynamic Reconfiguration Next Profile 0

Table 15.   dyn_rcfg_dr_next_profile_0_reg
Offset 0x04
Addressing Mode 32-bits
Description Dynamic reconfiguration control and status register.
Table 16.   dyn_rcfg_dr_next_profile_0_reg
Bit Type Reset Description
31:19 RO 0 Reserved
18 RW 0 Disable CPI Sequence
When set to 1, indicates that the dynamic reconfiguration controller does not execute the CPI sequence command for FGT transceiver channels adaptation.
Note: The simulation doesn't enable the FGT firmware by default. In simulation, you must set this bit to 1; otherwise, the simulation may fail.
17 RW 0 Start Up IP Restore Settings Indicator

Indicates the option to load the startup profile settings. Host software may use this field to load startup profile settings.

When firmware terminates with error, this requires a new DR trigger request. DR Nios® doesn't terminate this automatically. Along with this flag set to 1 to restore the startup IP settings, the host must program Next Profile ID for corresponding start up IP profile and Next Profile Indicator also set to 1. In this case, other IP settings for corresponding profile are ignored for startup IP.

Do not program this bit when Ready For Next Trigger is set to 0.

16 RW 0 Final State Profile Neutral Indicator

When set to 1, indicates that the final targeted profile to dynamically reconfigure into is Neutral state.

This bit, with the conjunction of the Enable Next Profile bit, differentiates between two scenarios for the final state condition:
  • state A > Neutral > state B
  • state A > Neutral

After you applied the new configuration setting, if the final state is Neutral, the Nios® system does not bring the relevant channel(s) out of reset prior to completing the dynamic reconfiguration flow.

Do not program this bit when Ready For Next Trigger is set to 0.

15 RW 0 Next Profile 0 Indicator
Indicates the Next Profile 0 status. The Nios® system determines the next DR step based on the status value. Available values are:
  • 1: Active profile—enables the profile settings from MIF contents corresponding to the next profile 0 ID.
  • 0: Neutral profile—enables the powerdown profile settings from MIF contents corresponding to the next profile 0 ID.

Do not program this bit when Ready For Next Trigger is set to 0.

14:0 RW 0 Next Profile 0

Indicates the client configuration profile to which you want to dynamically reconfigure your current profile. The Intel® Quartus® Prime software automatically assigns the profile numbers per each tile. The profile numbers are unique.

Setting Next Profile 0 to Profile ID 0 terminates the dynamic reconfiguration. You must ensure all previously assigned IDs are cleared to 0 before processing a new dynamic reconfiguration sequence.

You must ensure all fields are programmed correctly and all associated programming sequences can load and execute correctly.

Do not program this field when Ready For Next Trigger is set to 0.

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